Merging Control-flow and Dataflow Architectures on a Single Chip - Korolija, Nenad; Štrbac-Savić, Svetlana (Journal of Computer and Forensic Sciences, 2024)
Computing power rises predominantly by increasing the number of cores of modern processors, and the number of cores in cluster and cloud architectures. Along with increasing the processing power, high performance computing requirements also rise. Vast of the computing infrastructure includes control-flow processors that are based on von Neumann paradigm. In contrary, the principle of dataflow architectures is based on the data flowing through the already configured hardware. Dataflow architectures are often implemented using FPGAs. Recent research has proposed hybrid architectures, where both control-flow and dataflow hardware would exist on the same chip die. In this article, a new hybrid control-flow and dataflow architecture is proposed, where control-flow hardware would be similar to modern graphical cards, consisting of thousands of cores, but with a reasonable small amount of dataflow hardware available on each GPU core. The proposed architecture is tested by analyzing the conjugate gradient method executed on both control-flow and dataflow hardware. The execution of a the algorithm is divided onto GPU cores, and the execution of repeated instructions on each GPU core is delegated to the assigned dataflow hardware. Results indicate that it is possible to accelerate the execution of algorithms using the proposed architecture.
Keywords: dataflow; control-flow; GPU; high performance computing