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Abstract
In this paper, the implementation of a Finite Impulse Response (FIR) filter in the Residue Number System (RNS), is presented, in which a modulo multiplier based on the isomorphism technique is used to perform multiplication in the (2n+1) channel. An RNS modular multiplication in the Galois Field GF(2n+1) is presented in detail in this paper. The multiplication is based on the isomorphic mapping technique adapted to the residue arithmetic. The isomorphic encoder and decoder look-up tables in the GF(28+1) are given. An architecture for FIR filter design based on distributed arithmetic for multiplication and accumulation in mentioned (2n+1) channel is also presented. This architecture is discussed in details and compared with with architecture based on isomorphing technique.
Keywords
Multiplication
Lookup table
Modular arithmetic
Distributed arithmetic
References
Chen, G., Bai, G., & Chen, H. 2007. A New Systolic Architecture for Modular Division. IEEE Transactions on Computers, 56(2), pp. 282-286. doi:10.1109/tc.2007.20
Chen, R., Fan, J., & Liao, C. 2014. Reconfigurable Galois Field multiplier. In 2014 International Symposium on Biometrics and Security Technologies (ISBAST). Institute of Electrical and Electronics Engineers (IEEE)., pp. 112-115. doi:10.1109/isbast.2014.7013104
Jullien, 1980. Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms. IEEE Transactions on Computers, C-29(10), pp. 899-905. doi:10.1109/tc.1980.1675473
Kitsos, P., Theodoridis, G., & Koufopavlou, O. 2003. An efficient reconfigurable multiplier architecture for Galois field GF(2m). Microelectronics Journal, 34(10), pp. 975-980. doi:10.1016/s0026-2692(03)00172-1
NagaJyothi, G., & SriDevi, S. 2017. Distributed arithmetic architectures for FIR filters-A comparative review. In 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). Institute of Electrical and Electronics Engineers (IEEE)., pp. 2684-2690. doi:10.1109/wispnet.2017.8300250
Nannarelli, A., Cardarilli, G. C., & Re, M. 2003. Power-delay tradeoffs in residue number system. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..Institute of Electrical and Electronics Engineers (IEEE)., pp. 413-416. doi:10.1109/iscas.2003.1206300
Padmavathy, R., & Bhagvati, C. 2012. Discrete logarithm problem using index calculus method. Mathematical and Computer Modelling, 55(1-2), pp. 161-169. doi:10.1016/j.mcm.2011.02.022
Pradhan, 1978. A Theory of Galois Switching Functions. IEEE Transactions on Computers, C-27(3), pp. 239-248. doi:10.1109/tc.1978.1675077
Qi, H., Kim, Y., & Choi, M. 2012. A high speed low power modulo 2n + 1 multiplier design using carbon-nanotube technology. In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). Institute of Electrical and Electronics Engineers (IEEE)., pp. 406-409. doi:10.1109/mwscas.2012.6292043
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